? semiconductor components industries, llc, 2009 august, 2009 ? rev. 2 1 publication order number: NTMD4820N/d NTMD4820N power mosfet 30 v, 8 a, dual n ? channel, soic ? 8 features ? low r ds(on) to minimize conduction losses ? low capacitance to minimize driver losses ? optimized gate charge to minimize switching losses ? dual soic ? 8 surface mount package saves board space applications ? disk drives ? dc ? dc converters ? printers maximum ratings (t j = 25 c unless otherwise stated) rating symbol value unit drain ? to ? source voltage v dss 30 v gate ? to ? source voltage v gs 20 v continuous drain current r ja (note 1) steady state t a = 25 c i d 6.4 a t a = 70 c 5.1 power dissipation r ja (note 1) t a = 25 c p d 1.28 w continuous drain current r ja (note 2) t a = 25 c i d 4.9 a t a = 70 c 3.9 power dissipation r ja (note 2) t a = 25 c p d 0.75 w continuous drain current r ja t < 10 s (note 1) t a = 25 c i d 8.0 a t a = 70 c 6.4 power dissipation r ja t < 10 s (note 1) t a = 25 c p d 2.0 w pulsed drain current t a = 25 c, t p = 10 s i dm 32 a operating junction and storage temperature t j , t stg ? 55 to +150 c source current (body diode) i s 2.0 a single pulse drain ? to ? source avalanche energy t j = 25c, v dd = 30 v, v gs = 10 v, i l = 11 a pk , l = 1.0 mh, r g = 25 eas 60.5 mj lead temperature for soldering purposes (1/8 from case for 10 s) t l 260 c thermal resistance ratings rating symbol max unit junction ? to ? ambient ? steady state (note 1) r ja 97.5 c/w junction ? to ? ambient ? t 10 s (note 1) r ja 62 junction ? to ? foot (drain) r jf 40 junction ? to ? ambient ? steady state (note 2) r ja 167.5 1. surface ? mounted on fr4 board using 1 inch sq pad size, 1 oz cu. 2. surface ? mounted on fr4 board using the minimum recommended pad size. http://onsemi.com n ? channel 30 v 27 m @ 4.5 v 20 m @ 10 v r ds(on) max i d max v (br)dss 8 a device package shipping ? ordering information NTMD4820Nr2g soic ? 8 (pb ? free) 2500/tape & reel soic ? 8 case 751 style 11 4820n = device code a = assembly location y = year ww = work week = pb ? free package ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. 1 8 4820n ayww 1 8 marking diagram & pin assignment s1 g1 s2 g2 d1 d1 d2 d2 d g s
NTMD4820N http://onsemi.com 2 electrical characteristics (t j = 25 c unless otherwise noted)jk characteristic symbol test condition min typ max unit off characteristics drain ? to ? source breakdown voltage v (br)dss v gs = 0 v, i d = 250 a 30 v drain ? to ? source breakdown voltage tem- perature coefficient v (br)dss /t j 26 mv/ c zero gate voltage drain current i dss v gs = 0 v, v ds = 24 v t j = 25 c 1.0 a t j = 100 c 10 gate ? to ? source leakage current i gss v ds = 0 v, v gs = 20 v 100 na on characteristics (note 3) gate threshold voltage v gs(th) v gs = v ds , i d = 250 a 1.5 3.0 v negative threshold temperature coeffi- cient v gs(th) /t j 5.0 mv/ c drain ? to ? source on resistance r ds(on) v gs = 10 v i d = 7.5 a 15 20 m v gs = 4.5 v i d = 6.5 a 20 27 forward transconductance g fs v ds = 1.5 v, i d = 7.5 a 21 s charges, capacitances and gate resistance input capacitance c iss v gs = 0 v, f = 1.0 mhz, v ds = 15 v 940 pf output capacitance c oss 225 reverse transfer capacitance c rss 125 total gate charge q g(tot) v gs = 4.5 v, v ds = 15 v, i d = 7.5 a 7.7 nc threshold gate charge q g(th) 1.1 gate ? to ? source charge q gs 3.3 gate ? to ? drain charge q gd 3.2 total gate charge q g(tot) v gs = 10 v, v ds = 15 v, i d = 7.5 a 15.2 nc switching characteristics (note 4) turn ? on delay time t d(on) v gs = 10 v, v dd = 15 v, i d = 1.0 a, r g = 6.0 9.4 ns rise time t r 4.0 turn ? off delay time t d(off) 21 fall time t f 6.5 drain ? to ? source characteristics forward diode voltage v sd v gs = 0 v i d = 2.0 a t j = 25 c 0.75 1.0 v t j = 125 c 0.59 ns reverse recovery time t rr v gs = 0 v, d is /d t = 100 a/ s, i s = 2.0 a 17.8 charge time t a 8.3 discharge time t b 9.5 reverse recovery time q rr 8.0 nc package parasitic values source inductance l s t a = 25 c 0.66 nh drain inductance l d 0.20 nh gate inductance l g 1.50 nh gate resistance r g 1.5 3.0 3. pulse test: pulse width 300 s, duty cycle 2%. 4. switching characteristics are independent of operating junction temperatures.
NTMD4820N http://onsemi.com 3 typical performance curves t j = 125 c v ds , drain ? to ? source voltage (volts) i d, drain current (amps) figure 1. on ? region characteristics figure 2. transfer characteristics v gs , gate ? to ? source voltage (volts) figure 3. on ? resistance vs. gate ? to ? source voltage i d, drain current (amps) figure 4. on ? resistance vs. drain current and gate voltage figure 5. on ? resistance variation with temperature t j , junction temperature ( c) t j = 25 c t j = ? 55 c t j = 25 c i d = 7.5 a v gs = 10 v r ds(on), drain ? to ? source resistance (normalized) t j = 25 c r ds(on), drain ? to ? source resistance ( ) v gs = 10 v figure 6. drain ? to ? source leakage current vs. voltage v ds , drain ? to ? source voltage (volts) v gs = 0 v i dss , leakage (na) t j = 150 c t j = 100 c v gs = 4.5 v v ds 10 v 3.2 v 3.0 v i d, drain current (amps) 5 v 4.5 v 4 v 3.6 v 0 2.5 5 7.5 10 0 0.5 1.0 1.5 2.0 2.5 3.0 0 5 10 15 12 34 0 0.005 0.010 0.015 0.020 0.025 0.030 2 6 10 14 0.6 0.8 1.0 1.2 1.4 1.6 ? 50 ? 25 0 25 50 75 100 125 150 100 1000 10000 100000 3 6 9 12151821242730 3.4 v 2.8 v 10v 6 v 4.2 v 3.8 v 0.7 0.9 1.1 1.3 1.5 12.5 15 3.5 4.0 1.5 2.5 3.5 4.5 4812 v gs , gate ? to ? source voltage (volts) r ds(on), drain ? to ? source resistance ( ) t j = 25 c i d = 7.5 a 0.005 0.015 0.025 0.035 0.045 0.055 0.065 0.075 0.095 34 6 8 10 0.085 579
NTMD4820N http://onsemi.com 4 typical performance curves figure 7. capacitance variation figure 8. gate ? to ? source and drain ? to ? source voltage vs. total charge figure 9. resistive switching time variation vs. gate resistance figure 10. diode forward voltage vs. current drain ? to ? source voltage (volts) c, capacitance (pf) 300 0510 t j = 25 c c iss c oss c rss 15 25 0 1200 v gs = 0 v v gs , gate-to-source voltage (volts) q g , total gate charge (nc) i d = 7.5 a t j = 25 c v gs q gs r g , gate resistance (ohms) t, time (ns) v dd = 10 v i d = 1 a v gs = 15 v t r t d(on) t f t d(off) q gd qt 600 900 t j , starting junction temperature ( c) eas, single pulse drain ? to ? source avalanche energy (mj) i d = 11 a 20 figure 11. maximum rated forward biased safe operating area v ds , drain ? to ? source voltage (volts) i d , drain current (amps) r ds(on) limit thermal limit package limit v gs = 20 v single pulse t c = 25 c dc 10 ms 1 ms 100 s 10 s figure 12. maximum avalanche energy vs. starting junction temperature 1300 30 1 04 0 4 6 2 3 8 5 12 8 10 7 9 16 0 8 12 4 16 20 v ds , drain-to-source voltage (volts) v ds 100 1 10 100 1 1000 10 0.1 10 100 1 100 1 0.1 0.01 25 25 50 75 100 0 50 75 150 125 10 200 1100 500 800 100 1000 400 700 2 6 10 14 v sd , source ? to ? drain voltage (volts) i s , source current (amps) v gs = 0 v t j = 25 c 1 0.3 0.5 0.6 0.7 0 2 3 0.8 0.4
NTMD4820N http://onsemi.com 5 package dimensions soic ? 8 nb case 751 ? 07 issue aj seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751 ? 01 thru 751 ? 06 are obsolete. new standard is 751 ? 07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ? x ? ? y ? g m y m 0.25 (0.010) ? z ? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* style 11: pin 1. source 1 2. gate 1 3. source 2 4. gate 2 5. drain 2 6. drain 2 7. drain 1 8. drain 1 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2 ? 9 ? 1 kamimeguro, meguro ? ku, tokyo, japan 153 ? 0051 phone : 81 ? 3 ? 5773 ? 3850 NTMD4820N/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.
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